Conventionally, when a central processing unit (CPU) receives an interrupt from an interrupt controller, the CPU starts an interrupt processing handler corresponding to a cause of interrupt and performs interrupt processing.
FIG. 9 is a diagram illustrating an example of conventional interrupt processing. FIG. 9 illustrates a case in which input/output (IO) processing is performed for an interrupt from a device. As illustrated in FIG. 9, a CPU 93 is notified of a message signal interrupt (MSI) from devices 91a and 91b through an interrupt controller 92 as an interrupt (1).
Then, the CPU 93 calls an interrupt processing handler corresponding to the cause of interrupt in order to process the interrupt (2). Specifically, when the CPU 93 receives an interrupt notification from the device 91a, the CPU 93 calls an interrupt processing handler 94a, and when the CPU 93 receives an interrupt notification from the device 91b, the CPU 93 calls an interrupt processing handler 94b. 
Then, the interrupt processing handler 94a or 94b performs processing on hardware, such as clearing the cause of interrupt (3). Then, the interrupt processing handler 94a or 94b connects a command 95b corresponding to the cause of interrupt to an end of a command queue 95a of an IO task 95 (4). Then, the IO task 95 processes a first command 95b in the command queue 95a. 
There is a conventional technique in which a polling memory for storing information indicating the presence of interrupt is provided in a multi-processor system and a specified processor checks the polling memory (for example, see Japanese Laid-open Patent Publication No. 2006-216042). Further, there is a conventional technique in which a bridge apparatus detects an MSI that is written to a memory by a peripheral component interconnect (PCI) device, issues a new MSI, and causes another PCI device to receive the MSI (for example, see Japanese Laid-open Patent Publication No. 2010-117872).
In recent years, a CPU installed in a control apparatus such as redundant arrays of inexpensive disks (RAID) apparatus tends to include a plurality of CPU cores. Therefore, to improve performance of the control apparatus, it is a problem to perform interrupt processing by effectively using a plurality of CPU cores.